As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being—on and off the job.

Ciena’s WaveLogic family of products is a cornerstone of our optical fiber transmission solutions, driving innovation and success in the telecommunications industry. Partner with RTL circuit designers and other layout engineers to create optimal floorplans, design power grids, and clock distribution networks that achieve the best performance and power efficiency. Navigate and fine-tune EDA tool settings, parameters, and attributes to ensure signoff-quality results with an optimal balance of performance, power, and area (PPA).

Identify and propose alternative implementations, trade-offs, and solutions to achieve lower power consumption and higher performance. Collaborate with analog designers and ASIC/SoC teams to integrate analog blocks seamlessly into the overall design. Conduct initial Place & Route trials to refine design and correlation,



influencing circuit architecture by working closely with RTL designers and architects to ensure reliable and closable physical design.

Utilize tools like Formality or Conformal for formal verification, analyzing reports and ensuring design accuracy and integrity. Produce concise status reports at various stages of development, highlighting trade-offs and providing actionable insights.

Minimum

Bachelor’s degree in Electrical or Computer Engineering, Computer Science or other applicable scientific degree coupled with significant experience in ASIC physical digital design and timing closure Understanding of the submicron technology nodes full backend ASIC flow and timing/power/area analysis and trade-offs.

Experience with Static Timing Analysis (STA) medical, dental, and vision plans Employee Assistance Program (EAP) company-paid holidays vacation time We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence. Ciena is an Equal Prospect Employer, including disability and protected veteran status.

📌 DESIGN ENGINEER - CAD (Quebec)
🏢 Ciena
📍 Quebec