Design Verification Technical Lead (Quebec)

Design Verification Technical Lead (Quebec)

23 Oct
|
Advanced Micro Devices
|
Quebec

23 Oct

Advanced Micro Devices

Quebec

At AMD, we believe technology has the power to solve the world’s most key challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re redesigning next‑gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger— technology that moves the world forward.

This is a Technical Lead/Manager role for ASIC Hardware and Firmware Co-Verification Engineering role with the Security IP Team (SECIP) in AMD. The primary focus of this role is to Lead and Manage the team responsible for Hardware/Firmware co-verification of various embedded micro-processor subsystems and the associated hardware accelerators in leading edge SOC’s. These IP subsystems provide high performance functions to the respective SoC, such as security policy management, cryptography, data compression, high throughput DMA, etc.

The ideal candidate has experience leading others in technical and managerial settings. You also have excellent communication, writing, and presentation skills. Lead a high-performance engineering team Lead team, meet schedule commitments and provide strong support to customers Responsible to performance review , career development for team member .

Managed the team that is responsible for implementing / executing below task Develop and maintain subsystem verification architecture, testbench, test methodology for AXI/AHB busses and HW accelerators such as Cryptography, Data Compression, DMA, etc. Participate in subsystem specification, influence IP micro-architecture development (HW and FW co-design and verification aspect),



develop and verify abstracted performance model Create abstracted FW and HW performance models Develop critical target code to collect IP performance key parameters Explore subsystem architecture performance trade-off for FW and HW optimization Drive team to Develop and execute subsystem and block level test plans Develop and debug UVM and C-DPI test cases with integrated FW Further develop subsystem and block level testbenches using UVM randomized test methodology and C-DPI directed test methodology. Develop and maintain subsystem testbench build and test run scripts Strong mentoring and coaching skills Proven experience managing and leading engineering teams Prior experience in optimizing performance (client, server, system, or embedded) Strong system and software engineering background Strong analytic and problem-solving skills including the ability to analyze current behavior, identify potential areas for improvement and design of experiments Prior experience Managing technical teams ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

📌 Design Verification Technical Lead (Quebec)
🏢 Advanced Micro Devices
📍 Quebec

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