Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. This is a senior level position.

We are seeking a Senior Analog & Mixed-Signal Modelling Architect to join our DSP team. This position emphasizes behavioral modeling using C++ and SystemC, tightly integrated with MATLAB-based system simulations, firmware bring-up flows, and lab validation. You will operate at the intersection of analog-/digital-hardware, DSP, firmware, and electro-optical subsystems - contributing architectural decisions from early concept through silicon bring-up and product deployment.

Develop behavioral models of analog and mixed‑signal blocks using C++ and SystemC, with emphasis on firmware register‑map interfaces, control, observability, and execution speed rather than circuit‑level detail. Apply C++ / SystemC‑AMS to model continuous‑time and mixed‑signal behavior of PLLs, clocking systems, filters, DACs, ADCs, SerDes, and related subsystems. Build, support, and maintain C++ and MATLAB‑based verification flows, including C++ MEX wrappers that enable behavioral models to be exercised directly within system simulators.

Collaborate closely with analog, digital, DSP, firmware, and lab teams to align models, specifications, and validation plans. Support ASIC lab bring‑up and characterization, correlating silicon and lab data with behavioral models and system simulations. Proven experience writing C++ and/or SystemC behavioral models for hardware‑adjacent systems.

Demonstrated ability to operate at the system‑architecture level while remaining grounded in real analog behavior and physical impairments.



Solid understanding of key analog impairments, including noise, distortion, non‑linearity, bandwidth limitations, jitter, and phase noise, and their impact on modem‑level performance. Strong intuition for analog‑digital partitioning, power‑performance trade‑offs, and calibration strategies.

Comfortable translating loosely defined system goals into well‑bounded analog architectures and specifications. Ability to mentor engineers across disciplines and serve as a technical reference for analog signal‑processing decisions. Comfortable working in a Linux‑based development environment, using Git and modern cooperative workflows.

Clear technical communication skills and the ability to work effectively across disciplines. Post‑graduate degree in Physics or Engineering with a focus on ASIC hardware, communication systems, and/or control systems. C++, SystemC‑AMS MATLAB, Simulink Python Cadence Virtuoso Cadence AMS Designer Xcelium AMS The annual salary range for this position is $109,000 - $174,000 CAD.

Non‑Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company‑paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

📌 Senior Analog & Mixed-Signal Modelling Architect (Quebec)
🏢 Ciena
📍 Quebec