23 Oct
|
Ciena
|
Riviere-des-Prairies—Pointe-aux-Trembles
23 Oct
Ciena
Riviere-des-Prairies—Pointe-aux-Trembles
Ciena Corporation in Ottawa is seeking a hardware-focused ASIC design engineer to design mixed-signal macros within an ASIC flow for high-baud-rate optical modems.You will generate Verilog, SPICE netlists, and provide IP integration support, using Cadence and Synopsys tools. This role emphasizes analog/digital timing handoff and test methodologies.The team collaborates across analog and digital disciplines, applying rigorous design and verification practices.
📌 Mixed-Signal Ip Integration Engineer: High-Speed Asics (Riviere-des-Prairies—Pointe-aux-Trembles)
🏢 Ciena
📍 Riviere-des-Prairies—Pointe-aux-Trembles