Seeking a Senior ASIC Design Engineer for AI/HPC SOCs, involving system to spec translation and synthesis constraint development. Requires 8+ years of ASIC design experience, Verilog/System Verilog proficiency, and lab troubleshooting skills.
📌 Senior Asic Design Engineer – Rtl, Synthesis (North York)
🏢 Btadesignservices
📍 North York
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