Seeking a Senior ASIC Design Engineer to design power and area optimized functional blocks for high-speed connectivity products, involving RTL code creation, integration, testing, timing constraint crafting, and lab validation.
📌 Asic Design Engineer - Digital Dsp Design & Analog/Mixed-Signal - C$109,000 - C$174,000 A Year (Quebec City)
🏢 CELERO COMMUNICATIONS
📍 Quebec City
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