Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.Firmware at the boundary between hardware and software is where you have built your career. A single miscalculation can mean the difference between a memory interface that trains cleanly and one that fails in the field, and that reality has shaped how you work. Performance is not just about writing tight code. It is about understanding what the silicon is actually doing when your code runs at boot time.Dropping into RTL waveforms to debug firmware comes naturally to you. So does stepping back to question whether the algorithm itself needs rethinking. Profiling compiled code to find microcode level bottlenecks is the kind of work that keeps you engaged. The hardware is real, the constraints are real, and the problems do not solve themselves with abstractions.Mentoring others matters to you, but so does staying curious about how new modeling techniques might change what is possible.At Synopsys, the memory interface PHYs you work on will power the next generation of DDR, LPDDR, and HBM solutions.What You'll Be Doing Develop and optimize firmware for DDR, LPDDR, and HBM memory interface PHY training sequencesProfile compiled firmware at the instruction level to identify runtime bottlenecks and implement optimizations that improve training performanceAnalyze RTL waveforms and testchip data in the hardware lab to understand eye margin sensitivity and refine training algorithmsCollaborate with firmware architecture to study JEDEC protocol specifications and propose algorithmic improvements to training workflowsDebug complex hardware-software interaction issues across firmware, RTL,



and physical silicon using lab equipment and simulation toolsExplore and prototype how emerging modeling techniques could be applied to memory training workflowsMentor engineers on the team, sharing your knowledge of embedded firmware development, hardware debugging, and memory interface behaviorThe Impact You Will Have Reduce training runtime for next-generation memory PHYs, directly improving customer time-to-market and system boot performanceImprove training robustness and eye margin across process, voltage, and temperature corners, resulting in higher yield and reliability for customer designsInfluence the architecture of future PHY training algorithms by bringing fresh perspectives grounded in real hardware behaviorAccelerate team capability by mentoring engineers on low-level firmware optimization, RTL debugging, and protocol-level problem solvingEnable Synopsys to deliver competitive, high-performance memory IP solutions that meet the demands of AI, HPC, and data center applicationsShape the direction of firmware development practices and tooling within the IP Group through your technical leadershipContribute to the successful deployment of memory PHY IP used by leading semiconductor companies worldwideWhat You'll Need Bachelor's degree in Engineering, Computer Science, or related field with 12+ years of software development experience, Master's with 10+ years, or Ph D with 8+ years, all in commercial or production environmentsDeep proficiency in C for embedded firmware development, including experience optimizing for resource-constrained processorsHands-on experience with RTL waveform analysis and debugging using tools like Verdi, DVE, or similarDemonstrated ability to work at the hardware-software boundary,



understanding how firmware interacts with digital logic and physical interfacesExperience profiling and optimizing compiled code for performance-critical applicationsStrong debugging skills across firmware, RTL simulation, and hardware lab environmentsExperience with Python and Verilog is a strong plus, particularly for test automation and RTL co-developmentWho You Are When a training algorithm in a JEDEC spec catches your eye, your mind immediately goes to edge cases, corner conditions, and where the runtime cost will hideWorking in a hardware lab with testchips, probing signals, and correlating scope traces with firmware behaviour is second nature to youDebugging means profiling, tracing, and looking at waveforms until the root cause reveals itself, not guessing your way throughBringing ideas to the table is important to you, and so is being open to pushback or defending a position when it mattersExplaining a firmware optimization to a hardware engineer or a training strategy to a customer-facing team is something you can do without losing either audienceMentoring by showing is your style, walking someone through a debug session or profiling workflow until they can own it themselvesThe Team You'll Be Part Of You will be part of the Synopsys IP Group firmware development team based in Ottawa, focused on developing interface IP solutions for DDR, LPDDR, and HBM memory interfaces. The team works on the challenging problem of PHY-to-memory interface training for next-generation protocols and bus speeds, balancing runtime performance with quality of results. This is a team that values fresh perspectives and is committed to mentoring and integrating new members. You will have access to an advanced hardware lab with a library of testchips for real-world validation and optimization work.Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and advantages during the hiring process.#J-18808-Ljbffr

📌 Principal Firmware Engineer (Quebec City)
🏢 Synopsys
📍 Quebec City