Lead ASIC verification for Snap Inc.’s Spectacles Team, using UVM, SystemVerilog, and Siemens Questa in an office-based model.

This engineer designs verification for display Integrated Circuits supporting augmented reality. The work spans digital design, analog logic, software, and verification collaboration. You will build testbenches, execute coverage-driven plans, automate tools, and debug simulations.

Key Responsibilities:

- Design display Integrated Circuits for augmented reality
- Develop UVM-based and assertion-based testbenches
- Create functional and code coverage verification test plans
- Use Siemens Questa for verification and debugging
- Specify tools and create automation

Requirements:

- BSEE, MSEE, or relevant years of experience
- 10+ years of ASIC Design Verification experience
- Solid UVM and SystemVerilog knowledge
- Digital simulation and Verilog RTL practices
- Linux scripting with TCL, Make, Perl, Python, or Shell

Apply ASIC verification expertise, coverage planning, SystemVerilog, and automation to Snap’s AR display circuit development.

📌 Senior ASIC Design Verification Engineer (Vancouver)
🏢 Snap
📍 Vancouver