Shape SerDes IP architecture at Synopsys through transistor-level design, advanced verification, and technical leadership across analog macro circuits. Mentor engineers while optimizing high-speed interfaces.

As an experienced Analog Circuit Architect, you will own analog macro-level circuits for SerDes IP and guide sub-block progress. You will interpret standards, define specifications, and balance power, area, and performance. The work spans silicon-proven TX, RX, and clock paths, FinFET CMOS layout, SPICE analysis, and Verilog-A modeling.

Key Responsibilities:

- Own SerDes analog macro architecture, design, and implementation
- Track sub-block owners and review technical progress
- Translate standards into detailed analog specifications




- Optimize circuits for power, area, and performance
- Present simulations and insights during peer and customer reviews

Requirements:

- PhD with 10+ years or MSc with 12+ years’ experience
- Expertise in transistor-level and CMOS circuit design
- Silicon-proven TX, RX, and clock path implementation
- Leadership experience guiding small design teams
- Proficiency with EDA tools, SPICE, and Verilog-A

Apply your SerDes architecture, analog design, verification, and leadership expertise to Synopsys semiconductor IP development.

📌 Senior SerDes Analog Circuit Architect (Montreal)
🏢 Synopsys
📍 Montreal