Integrated Circuit Design Verification Engineer (Vancouver)

Integrated Circuit Design Verification Engineer (Vancouver)

22 Oct
|
Snap
|
Vancouver

22 Oct

Snap

Vancouver

Integrated Circuit Design Verification Engineer Snap Inc is a technology company. We believe the camera presents the greatest opportunity to improve the way people live and communicate. Snap contributes to human progress by empowering people to express themselves, live in the moment, learn about the world, and have fun together.

The Company operates Snapchat , a visual messaging app that enhances your relationships with friends, family, and the world, and Specs Inc. , a wholly-owned subsidiary dedicated to making computing more human, in addition to Bitmoji , Saturn, and other digital services.

Specs Inc. is a wholly-owned subsidiary of Snap Inc. dedicated to making computing more human. The company develops Specs, advanced eyewear that seamlessly integrates digital experiences into the physical world.

Specs feature see-through lenses that place digital objects directly into three-dimensional space, powered by Snap OS, a proprietary, context-aware operating system designed for natural interaction with your hands and voice.

Specs Inc. also provides Lens Studio, a full suite of advanced developer tools that powers immersive augmented reality experiences across Specs, Snapchat, and other services.

We’re looking for a Integrated Circuit Design Verification Enginee r to join the Spectacles Team at Snap Inc

What you’ll do:

Work as part of a multi-disciplinary team designing display Integrated Circuits for AR

Work closely with digital design, analog logic, software and verification engineers

Develop and implement UVM-based and assertion-based testbenches

Create and execute verification test plans, including functional coverage and code coverage

Utilize Siemens Questa tool set for verification and debug tasks





Specify and configure tools and create automation

Knowledge, Skills & Abilities:

Strong knowledge of UVM and SystemVerilog for advanced verification methodologies

Strong knowledge of digital functional simulation, and tools such as Siemens Questa

Strong knowledge of good Verilog RTL coding practices

Scripting and automation, such as TCL, Make, Perl, Python and Shell scripts in Linux workplace

Excellent written and verbal English communication

Minimum Qualifications:

BSEE or MSEE or relevant years of experience

10+ years of experience in ASIC Design Verification

Preferred Qualifications:

Experience with entire verification process from planning to sign-off

Experience with Siemens’ UVM Framework

Experience in emulation

Experience in RTL design

Familiarity with video and display systems, MIPI, AMBA, I2C, SPI protocols and embedded microcontroller

Familiarity with ASIC test or production flow

Ideal candidate is a self-starter, can organise complex issues and drive them to closure

Able to multitask and prioritise.

Default Together Policy at Snap: At Snap Inc. we believe that being together in person helps us build our culture faster, reinforce our values, and serve our community, customers and partners better through dynamic collaboration. To reflect this,



we practice a "default together" approach and expect our team members to work in an office 4+ days per week.

At Snap, we believe that having a team of diverse backgrounds and voices working together will enable us to create cutting-edge products that improve the way people live and communicate. Snap is proud to be an equal opportunity employer, and committed to providing employment opportunities regardless of race, religious creed, color, national origin, ancestry, physical disability, mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, pregnancy, childbirth and breastfeeding, age, sexual orientation, military or veteran status, or any other protected classification, in accordance with applicable federal, state, and local laws. EOE, including disability/vets.

We are an Equal Opportunity Employer and will consider qualified applicants with criminal histories in a manner consistent with applicable law (by example, the requirements of the San Francisco Fair Chance Ordinance and the Los Angeles Fair Chance Initiative for Hiring, where applicable).

Our Benefits : Snap Inc. is its own community, so we’ve got your back We do our best to make sure you and your loved ones have everything you need to be happy and healthy, on your own terms. Our benefits are built around your needs and include paid parental leave, comprehensive medical coverage, emotional and mental health support programs, and compensation packages that let you share in Snap’s long-term success

Compensation

In the United States, work locations are assigned a pay zone which determines the salary range for the positi

📌 Integrated Circuit Design Verification Engineer (Vancouver)
🏢 Snap
📍 Vancouver

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