Lead HUB and Router verification at AMD, applying system architecture expertise and AI-enabled methods to complex silicon designs. The position is full-time.

As Principal Design Verification Engineer, you will provide technical leadership for AMD’s IOHUB front-end IP verification team. You will define scalable verification strategies, collaborate across architecture, design, emulation, firmware, and AI tooling, and improve productivity through automation and data-driven methods. The work supports server, data center, client, and embedded products.

Key Responsibilities

Own HUB and Router design verification test plans and methodologies

Build end-to-end strategies with architecture and engineering partners

Lead AI-assisted regression, coverage, stimulus, and debug initiatives

Guide usable workflows, success metrics,



and responsible tool adoption

Mentor engineers and address verification closure risks early

Requirements

Robust design verification expertise in architecture or related areas

Experience with AI-enabled engineering workflows is valued

Knowledge of scripting, data analysis, or automation frameworks

Command of coverage-driven, constrained-random, formal, and emulation methods

Bachelor’s or Master’s degree in a related engineering discipline

Apply design verification leadership, AI-enabled engineering, and system architecture expertise to advance AMD IOHUB silicon verification.

📌 Principal Design Verification Engineer (Markham)
🏢 Amphenol ICC
📍 Markham