Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? People come to work at Microchip because we help design the technology that runs the world. We take pride in our commitment to employee development, values-based decision making, and robust sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation.

The Mixed Signal Development

Group is responsible for delivering high performance analog, digital and mixed-signal IP to various divisions within Microchip. As a member of the Mixed-Signal Development Group, you will be working closely with architects, other digital design engineers, verification engineers, firmware engineers, and cross-functional teams. You will contribute to the RTL design and verification of DDR or flash controller/PHY subsystem blocks, playing a key role throughout the ASIC development lifecycle.

Participate in the full ASIC design cycle, including design, verification, backend implementation, silicon bringup and debugging. Design RTL using Verilog/SystemVerilog, integrate IP blocks,



and implement supporting logic (e.g., Run clock domain crossing (CDC) analysis, lint check and power simulations. debug design and simulation issues. Work closely with backend team on STA timing closure, help analyze timing critical paths and resolve STA timing issues; Run trial synthesis to estimate logic depth and area early in the design cycle.

Work closely with Product Engineering team on characterization planning and execution as well as DFT related tasks, create test plans, test configuration, and provide debug support. Produce high-quality design, verification, and test documentation. Bachelor’s/Master’s/PhD in Electrical Engineering, Computer Engineering/Science, or related field ~Strong experience in RTL design and verification using Verilog, SystemVerilog, or VHDL ~ Experience or Knowledge in C/C++ and scripting/automation (Python, Perl, TCL, Shell) ~ Working knowledge of DDR and Flash Controller/PHY/memory considered an asset ~ Travel Time It consists of competitive base pay, restricted stock units, and quarterly bonus payments.

In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading IESPP program with a 6-month look back feature.

📌 Principal RTL Design Engineer (Burnaby)
🏢 HVAC Total FM Recruitment
📍 Burnaby