O-HIVE is a technology company developing next-generation Visual Language Model (VLM) intelligence, spatial vision systems, and specialized AI semiconductors for robotics, industrial automation, and autonomous systems.

Our technology enables machines to perceive their surroundings, recognize objects, understand spatial relationships, and make intelligent decisions in real time. By combining advanced computer vision, 3D spatial processing, and edge AI acceleration, O-HIVE is building compact, high-performance computing solutions that operate directly on embedded hardware.

We are developing a dedicated Spatial Vision ASIC architecture that integrates visual feature extraction, mapping, pose estimation, object detection, and VLM inference into an energy-efficient semiconductor platform.

Position Overview

About O-HIVE

O-HIVE is a technology company developing next-generation Visual Language Model (VLM) intelligence, spatial vision systems, and specialized AI semiconductors for robotics, industrial automation, and autonomous systems.

Our technology enables machines to perceive their surroundings, recognize objects, understand spatial relationships, and make intelligent decisions in real time. By combining advanced computer vision, 3D spatial processing, and edge AI acceleration, O-HIVE is building compact, high-performance computing solutions that operate directly on embedded hardware.

We are developing a dedicated Spatial Vision ASIC architecture that integrates visual feature extraction, mapping, pose estimation, object detection, and VLM inference into an energy-efficient semiconductor platform.

Position Overview





We are seeking a talented and motivated FPGA Engineer to join our engineering team and contribute to the development of hardware-accelerated spatial vision and edge AI systems.

The successful candidate will design, implement, and optimize FPGA-based processing architectures for real-time computer vision, simultaneous localization and mapping (SLAM), object detection, and AI inference.

This position involves working closely with AI researchers, software engineers, embedded systems developers, and ASIC designers to transition computationally intensive algorithms into efficient hardware implementations.

The engineer will play an important role in developing FPGA prototypes and supporting their eventual transition into production ASIC designs.

Key Responsibilities1. FPGA Architecture & RTL Development

- Design and implement FPGA-based accelerators using Verilog, SystemVerilog, VHDL, or High-Level Synthesis (HLS).
- Develop effective hardware processing pipelines for real-time image processing and AI workloads.
- Optimize FPGA designs for latency, throughput, power consumption, and resource utilization.
- Implement memory interfaces, hardware buffers, data movement architectures, and parallel processing pipelines.
- Perform functional simulation, synthesis,



timing analysis, and hardware verification.

Spatial Vision & SLAM Acceleration

- Develop hardware acceleration for visual feature extraction, including FAST, ORB, and related computer vision algorithms.
- Implement FPGA-based image preprocessing, feature matching, and geometric computation.
- Support hardware acceleration of visual odometry, mapping, and camera pose estimation.
- Integrate FPGA processing pipelines with SLAM frameworks such as ORB-SLAM3.
- Develop low-latency processing architectures for real-time navigation and 3D spatial awareness.

AI & VLM Hardware Acceleration

- Work with AI engineering teams to implement hardware-accelerated object detection and visual intelligence workloads.
- Support the deployment and optimization of YOLO-family detection models and lightweight VLM architectures.
- Develop efficient data paths for neural network computation and inference.
- Explore quantization and reduced-precision computation techniques, including INT8, INT4, and FP8.
- Optimize parallel computation, memory access, and accelerator utilization for resource-constrained edge devices.

Camera & Sensor Integration

- Develop FPGA interfaces for CMOS image sensors using MIPI CSI-2 and other high-speed interfaces.
- Implement image sensor control, pixel processing, frame buffering, and image data pipelines.
- Integrate inertial measurement units (IMUs) and other sensors into spatial vision processing architectures.
- Develop hardware-level timestamp synchronization between image frames and motion sensor dat

📌 FPGA AI Accelerator Engineer (Windsor)
🏢 O-HIVE.AI
📍 Windsor