Rtl/Fpga Design Engineer - C$110 - C$135 An Hour (Boucherville)

Rtl/Fpga Design Engineer - C$110 - C$135 An Hour (Boucherville)

21 Oct
|
LanceSoft
|
Boucherville

21 Oct

LanceSoft

Boucherville

Seeking an experienced RTL/FPGA Design Engineer with 15+ years in ASIC design, Verilog/System Verilog, and familiarity with networking protocols. Must have skills in RTL synthesis, CDC analysis, and scripting languages.

📌 Rtl/Fpga Design Engineer - C$110 - C$135 An Hour (Boucherville)
🏢 LanceSoft
📍 Boucherville

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