Must: design verification engineers with GLS (Gate level simulation), UVM, PCIe, UCIe, ethernet verification experience

ASIC Programs (Switch/NIC) DV

- Lead or contribute to verification of 4-5 ASIC design blocks.
- Develop UVM-based verification environments, sequences, tests, debug, and coverage closure.
- Solid experience in SystemVerilog/UVM and GLS
- Experience with PCIe, UCIe 2.0, and Ethernet protocols.
- Ability to independently own verification deliverables.
- Support customer collaboration in EST timezone.

Required Skills

- Strong SystemVerilog/UVM verification experience
- Knowledge and/or hands-on experience with:

o UCIe 2.0

o PCIe

o Ethernet

- Ability to own design blocks independently and drive verification closure

Responsibilities

The DV team is expected to:

- Own verification of 4-5 design blocks per ASIC
- Develop and execute sequences
- Perform test development and debug
- Drive coverage collection and closure
- Own end-to-end verification execution for assigned blocks
- The customer will own the testbench infrastructure.

#INDCAN

📌 Design Verification Engineer with GLS (gate level simulation) (Canada)
🏢 W3Global Canada
📍 Canada