Company

Qualcomm Canada ULC

Job Area

Engineering Group, Engineering Group > ASICS Engineering

General Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

Minimum Qualifications

- Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.

OR

Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

About The Role

We are seeking a Senior Staff Design Verification Engineer to lead verification architecture and execution for DSP products, high-speed SerDes integration, full-chip SoC verification, and pre-silicon ATE functional test validation. This role will drive verification closure from test planning and UVM environment development through production-oriented ATE vector signoff and post-silicon bring-up support.

What You'll Do

- Architect, develop, and maintain scalable SystemVerilog/UVM verification environments for DSP products,



SerDes subsystems, SoC interconnects, and full-chip integration.
- Lead verification of DSP functionality, datapaths, control logic, configuration, performance modes, error handling, and system-level integration.
- Verify SerDes integration, including calibration flows, CDR/PLL control, equalization, lane configuration, deskew, loopback, and digital interface behavior.
- Own SoC-level verification planning and closure for reset/boot flows, clocking, power states, interrupts, CDC/RDC, register access, and high-speed datapaths.
- Lead ATE functional test development across DSP, SerDes, SoC, and related hardware subsystems, including simulation, debug, qualification, and production vector signoff.
- Partner with Design, DFT, Firmware, Silicon Validation, Product Engineering, and ATE teams to transition test content from simulation to silicon and production environments.
- Drive metric-based verification closure across functional coverage, code coverage, assertions, and regression results.
- Debug complex multi-clock, multi-power-domain, RTL, testbench, firmware, and system integration issues.
- Provide technical leadership, mentor engineers, and improve regression efficiency, automation, and debug methodologies.

What You'll Need

- 10+ years of ASIC/SoC design verification experience.




- Strong hands-on expertise with SystemVerilog and UVM, including testbench architecture, sequences, agents, monitors, scoreboards, checkers, and coverage development.
- Experience verifying DSP products, complex SoC subsystems, full-chip integration, and high-speed interfaces.
- Solid understanding of SerDes digital integration, including PMA/PCS interfaces, calibration, training, equalization, clocking, resets, and lane management.
- Experience developing or validating functional test content for ATE, production test, silicon bring-up, or post-silicon validation.
- Proficiency with industry-standard simulation, debug, and coverage tools such as VCS/Verdi, Xcelium, or Questa.
- Strong scripting and automation skills using Python, Perl, Bash, Make, or similar tools.
- Proven ability to lead technical execution across cross-functional and geographically distributed teams.

Preferred Qualifications

- Experience with DSP architectures, signal-processing datapaths, communications products, or high-throughput data processing blocks.
- Knowledge of high-speed protocols such as PCIe, CXL, Ethernet, or custom multi-gigabit PHYs.
- Experience correlating pre-silicon simulation results with post-silicon lab validation or ATE fallout.
- Familiarity with UPF-based power-aware simulation and formal/property verification using SVA or JasperGold.
- Experience improving regression infrastructure, failure triage, and automated debug workflows.

Applicants

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring proc

📌 Design Verification Engineer, Senior Staff (Canada)
🏢 MaC VC
📍 Canada