Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? People come to work at Microchip because we help design the technology that runs the world. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. The Architecture Co-Verification team (ACOV) is an exciting, fast paced team responsible for enabling HW/FW development and co-verification of state-of-art System-On-Chip (SoC) devices using industry leading HW emulators (such as Cadence Palladium and Protium). The team is deployed in all aspects of SoC development phases from architectural exploration to post-silicon validation, HW/FW co-development, pre-silicon functional co-verification, pre/post-silicon performance testing, power analysis, and critical post-silicon investigations. As a Principal Design Engineer, you will be working closely with hardware designers, firmware engineers, and verification teams throughout the SoC development process. Porting SoC RTL to industry leading HW emulators and FPGA platforms. Developing common test ecosystem across pre/post silicon. Developing FW and tests for pre-silicon subsystem/system level co-verification. Troubleshoot and resolve complex problems in embedded multi-core real-time systems executing emulation test plans. Utilize state of the art protocol analyzers for analysis and error injection.



Utilization of test and defect tracking tools to document and report on verification progress and product quality. Effectively present technical information to small teams of engineers. BS/MS degree or higher in Electrical/Electronic Engineering or Computer Engineering. ~10+ years of relevant work experience. ~Knowledge of key components of a server and storage solution including Windows/Linux host driver architectures. ~ Proficient Linux experience and strong programming/scripting skills with languages such as C, Python, Tcl and Bash. ~ Proficient in digital design, RTL coding with VHDL, Verilog, or System Verilog experience. ~ Creation & management of system validation testing schedules and their execution. ~ Knowledge of MIPS, ARM, or RISC-V architecture, including JTAG, I2C, and firmware programming. Highly motivated team player who sets personal goals and achieves those goals without supervision. Experience with RAID HBA’s, SAS Controllers and their associated Software Testing Strategies in an asset. Experience with test automation, testing methodologies, and test tools Isolation and resolution of complex software & firmware problems in embedded real-time systems. Knowledge of Embedded Linux development as well as RTOS constructs including processes, threads, scheduling, synchronization mechanisms, memory management. Cadence infrastructure support and process flows is an asset. Travel Time It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health perks that begin day one, retirement savings plans, and an industry leading IESPP program with a 6-month look back feature.

📌 Engineer/Engineering Manager (Canada)
🏢 Microchip Technology
📍 Canada