Our client is seeking a highly technical Principal Engineer / Technical Lead with deep Memory PHY, SerDes PHY and mixed-signal design expertise.

Important: This is not a hands-on circuit design position. The ideal candidate comes from a strong technical design background but is ready to provide broader architectural and technical leadership across PHY IP, SoC integration, SI/PI, validation and production..

What You'll Own

Technical ownership of third-party Memory/SerDes PHY and mixed-signal IP

Lead IP from architecture and specification through SoC integration, validation and production

Drive performance, power and area (PPA) trade-off decisions

Provide technical leadership around signal integrity and power integrity (SI/PI)

Define and review IP specifications and integration requirements

Work closely with SoC teams, IP vendors and technical stakeholders

Support first-silicon bring-up, debug, characterization and compliance

Evaluate next-generation PHY and mixed-signal technologies

Ideal Background





Deep Memory PHY or SerDes PHY architecture knowledge

Ability to evaluate PPA trade-offs

Experience defining technical/IP specifications

Strong understanding of SoC integration processes

Knowledge of HBM, DDR, LPDDR, GDDR, PCIe, Ethernet, USB or related protocols

Experience with advanced semiconductor technologies

Post-silicon/debug experience is an asset

B.S./M.S. in Electrical Engineering or related discipline preferred

The Key Profile

We are looking for someone who has been deeply technical and close to design, particularly analog/mixed-signal design, but who can now operate above the individual design-block level.

Memory PHY experience is ideal; solid SerDes PHY experience is equally relevant.

The position can be remote anywhere in Canada or the U.S., although candidates able to work onsite or hybrid with engineering teams are preferred

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📌 Principal Engineer – Memory PHY / SerDes Architecture (Toronto)
🏢 TALENT TO HIRE
📍 Toronto