Elevate your career as a Memory Layout Technology Lead with Infosys in Vancouver, BC. Collaborate closely with circuit teams to drive optimal memory layout designs based on schematics.
At Infosys, we're seeking an experienced qualified with a minimum of 5 years in Compiler and Custom Memory Layout design. This role requires collaboration with our Registers and Memory Arrays team to improve memory architectures and enhance layout performance. You’ll engage in top-level integration and physical verification, ensuring layout precision.
Key Responsibilities:
• Design memory leafcell layout libraries from scratch
• Integrate layouts effectively with top levels
• Collaborate with engineers on schematic-driven designs
• Optimize layouts for maximum performance
• Conduct thorough physical verification and debugging processes
Requirements:
• Bachelor’s degree or 3 years of relevant experience
• Minimum 4 years in Information Technology
• Strong knowledge of FinFET technology
• Proficient in Cadence Virtuoso and Calibre verification
• Must be eligible to work in Canada without sponsorship
Embark on a journey of innovation in memory layout with Infosys.
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📌 Memory Layout Technology Lead at Infosys (Burnaby)
🏢 Infosys
📍 Burnaby