Synopsys Inc in Ottawa is seeking a senior package design engineer to lead IP test-chip packaging initiatives. You’ll drive 4–6 test-chip package designs annually from requirements through delivery, collaborating with internal teams, customers, and partners to optimize SI/PI performance.
You’ll apply 3D EM modeling with HFSS, define layer stacks, and guide customers through architecture evaluations, balancing electrical performance with manufacturability and cost. English communication required.