Elevate your career with Ciena as an ASIC Synthesis Engineer. Shape high-speed networking solutions while executing critical front-end implementation tasks in a cooperative, diverse setting.Ciena seeks an ASIC Synthesis Engineer to drive frontend implementation of cutting-edge ASIC technology. This role involves synthesis, static timing analysis, and clock domain validation that are vital for Ciena's optical networking solutions. Candidates should possess knowledge in the ASIC development process and have a solid grasp of logical equivalence checking and timing constraints.Key Responsibilities:
Execute frontend implementation for assigned IP subsystems
Develop timing constraints for synthesis and signoff
Perform logical equivalence verification during pre/postlayout stages
Validate clock domain crossings for ASIC integration
Create and optimize scripts enhancing workflowsRequirements:
B.Sc. in Electrical/Computer Engineering or related field
Knowledge of ASIC implementation flows
Familiarity with RTL design principles
Ability to work within multidisciplinary teams
Experience in managing project deliverablesContribute your expertise to high-performance optical networking at Ciena, making an impactful difference.#J-18808-Ljbffr