Elevate your career as a Memory Interface Validation Engineer with Synopsys, where you'll validate cutting-edge hardware designs. Join our Nepean laboratory to enhance AI-powered products through rigorous engineering solutions.

Synopsys is seeking a skilled engineer with 6-8+ years of experience in hardware design and validation for high-speed systems. Your expertise in Cadence Allegro, signal integrity analysis, and debugging will ensure optimal performance in our memory interface designs. Expect to collaborate with firmware and design teams to validate hardware reliability in production environments.

Key Responsibilities:
• Design and validate PCB layouts in Cadence Allegro
• Conduct signal integrity analysis on high-speed interfaces




• Debug systems with logic analyzers and oscilloscopes
• Engage in cross-functional design reviews
• Execute root cause analysis on validation challenges

Requirements:
• Bachelor's or Master's in Electrical Engineering
• 6-8+ years in hardware validation and design
• Proficient in Cadence Allegro and signal integrity principles
• Solid debugging skills with multiple analyzers
• Familiarity with JTAG, I2C, SPI, and UART interfaces

Leverage your technical skills in hardware validation to impact critical engineering projects at Synopsys.
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📌 Memory Interface Validation Engineer at Synopsys (Quebec City)
🏢 Synopsys
📍 Quebec City