Drive advanced analog layout design with Celero Communications as a High-Speed Analog Layout Design Engineer. This role focuses on the layout of mixed-signal IP blocks for cutting-edge AI infrastructure.

As a pivotal member of the Analog & Mixed-Signal design team, you will lead the design of complex analog blocks, such as ADCs and DACs. Collaborating closely with circuit designers and guiding junior engineers, your contributions will be essential to achieve silicon success. You will utilize industry-standard verification tools while promoting best practices in a rapidly evolving workplace.

Key Responsibilities:



• Lead physical layout design of analog/mixed-signal macros • Collaborate on layout solutions for performance and reliability • Mentor junior engineers on layout design best practices • Perform layout verification checks using industry-standard tools • Contribute to chip-level planning and integration

Requirements: • 10+ years in analog/mixed-signal layout design • Leadership in IP layout macros and FinFET technologies • Experience with TSMC FinFET process nodes • Strong understanding of device physics and layout effects • Proficiency in Cadence Virtuoso and verification tools

Leverage your expertise to shape high-performance semiconductor designs at Celero Communications. #J-18808-Ljbffr

📌 Lead Analog Layout Engineer at Celero (Montreal)
🏢 CELERO COMMUNICATIONS
📍 Montreal