Lead verification efforts at Qualcomm as a Senior ASIC/FPGA Design Verification Engineer. This role emphasizes high-speed interconnect protocols and deep technical leadership for innovative product development.

As a key player in Qualcomm's Engineering Group, you will utilize your expertise in ASIC design and verification. Your focus will be on developing scalable verification environments and driving closure on functional and coverage goals. Collaborating with cross-functional teams, you will ensure successful execution of high-performance products.

Key Responsibilities:
• Deliver standards-compliant IP blocks for high-speed ASICs
• Architect and document robust verification environments
• Develop comprehensive test plans and drive verification closure




• Mentor engineers to uphold verification best practices
• Drive issue resolution from discovery to closure

Requirements:
• MSc/MEng with 7+ years or BSc/BEng with 10+ years in verification
• Deep knowledge of PCIe, CXL, UALink, and Ethernet protocols
• Expert-level experience in SystemVerilog and UVM
• Solid problem-solving and communication skills
• Ability to influence cross-functional technical direction

Leverage your technical excellence and leadership skills to shape the future of communication technologies at Qualcomm.
#J-18808-Ljbffr

📌 Senior ASIC/FPGA Design Verification Engineer (Quebec City)
🏢 QUALCOMM
📍 Quebec City