ADVANCE YOUR CAREER. ADVANCE THE WORLD.At AMD, we believetechnology has the power to solve the world’s most significant challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward. Join us and, together, we’ll advance your career.ROLE SUMMARY:Own full-chip static timing analysis (STA) and timing closure for complex So C designs, fromearly design netlist through final signoff. Partner closely with Pn R, synthesis/DFT, and CADteams to drive timing convergence, methodology improvements, and flow automation across thebusiness unit.KEY RESPONSIBILITIES:Timing Closure & SignoffOwn full-chip timing closure across setup, hold, and DRV (transition/capacitance/noise) signoffDrive multi-corner/multi-mode (MMMC) timing convergence across PVT corners and modesAnalyze and resolve SI/crosstalk, OCV/POCV, and clock-related (skew, jitter, uncertainty) impacts on timingPerform root-cause analysis of timing violations and drive fixes through ECO, Pn R trials etc.Generate, validate, and hand off ECOs to Pn R PD teams; verify legalization andpost-ECO Qo RClock ArchitectureGuide clock tree build strategy across multiple methodologies (H-tree, MSCTS/multi-source CTS, clock mesh)Define clock structure and skew/latency targets in partnership with clock architecture and PD teamsCross-Team CollaborationWork with Pn R engineers to drive timing convergence at each implementation stage (place, CTS, route, ECO)Provide SDC (constraint) analysis, quality review,



and feedback to design and synthesis teamsFeed back repeater/floorplan/design guidance across So C based on timing analysisAnalyze run data and provide actionable feedback to PD execution teamsCollaborate across business units, CAD, and central methodology teams to define and drive requirementsInterface with other PPA (or equivalent) teams internal to AMD on cross-cutting timing topicsMethodology & AutomationDefine and drive common STA methodology and signoff criteria across the business unitBuild automation to streamline design signoff checks, Qo R tracking, and dashboard generationIdentify and adopt best practices from across AMD and industry to continuously improve flow/project best practicesDrive stage-by-stage improvements in competitiveness (PPA, turnaround time) of the AMD design flowCommunicationOrganize and present complex technical timing data clearly and concisely to technical and management audiencesDocument methodology, flows, and known issues for broader team consumptionREQUIRED QUALIFICATIONS:BS/MS/Ph D in Electrical Engineering, Computer Engineering, or related fieldFull chip timing experience preferredLocation:Markham, ONBenefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.

📌 Static Timing Analysis / Full Chip Timing Engineer (Markham)
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📍 Markham