A LEC (Logic Equivalence Checking) CAD Engineer who will develop and support formal equivalence methodologies to ensure functional correctness between RTL, synthesized netlists, and physical designs in complex SoC (System on a Chip) development
Key Responsibilities
Flow Management: Own and maintain end-to-end LEC sign-off methodologies across RTL-to-GDS and gate-to-gate flows.
ECO Implementation: Enable Engineering Change Order (ECO) flows to ensure secure, correct late-stage design modifications.
Debugging & Root Cause: Analyze and resolve non-equivalences, aborts, and mismatches across design stages.
Automation: Write and maintain scripts and automation infrastructure using Tcl, Python, Perl, or Shell.
Tool Optimization: Optimize runtime, capacity, and scalability of verification tools while partnering with EDA vendors.
AI Enablement : Enable AI enabled tools and methodologies
Core Requirements
Tools Knowledge: Proficiency in industry-standard tools like Cadence Conformal (LEC/ECO) and Synopsys Formality.
Education: Bachelor's or Master’s degree in Electrical Engineering, Computer Science, or related fields with dedicated hardware/EDA experience