Senior Rtl/Fpga Design Eng - Verilog, Vivado, Cdc (Contract) - C$110 - C$135 An Hour (Ottawa)

Senior Rtl/Fpga Design Eng - Verilog, Vivado, Cdc (Contract) - C$110 - C$135 An Hour (Ottawa)

16 Oct
|
LanceSoft
|
Ottawa

16 Oct

LanceSoft

Ottawa

Seeking an experienced RTL/FPGA Design Engineer with Verilog, Vivado, and CDC skills for a contract role. Requires a bachelor's degree and over 15 years of experience in RTL design.

📌 Senior Rtl/Fpga Design Eng - Verilog, Vivado, Cdc (Contract) - C$110 - C$135 An Hour (Ottawa)
🏢 LanceSoft
📍 Ottawa

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