Senior Rtl/Fpga Design Eng - Verilog, Vivado, Cdc (Contract) - C$110 - C$135 An Hour (Boucherville)

Senior Rtl/Fpga Design Eng - Verilog, Vivado, Cdc (Contract) - C$110 - C$135 An Hour (Boucherville)

16 Oct
|
LanceSoft
|
Boucherville

16 Oct

LanceSoft

Boucherville

Seeking an experienced RTL/FPGA Design Engineer with expertise in Verilog, Vivado, and CDC for a contract role in the semiconductor industry. Requires 15+ years of experience and a Bachelor's degree.

📌 Senior Rtl/Fpga Design Eng - Verilog, Vivado, Cdc (Contract) - C$110 - C$135 An Hour (Boucherville)
🏢 LanceSoft
📍 Boucherville

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Get the latest job offers by email for: senior rtl/fpga design eng - verilog, vivado, cdc (contract) - c$110 - c$135 an hour (boucherville) / boucherville