Qualcomm Canada ULC is seeking a senior ASIC Physical Design engineer to lead end‑to‑end PD flows for So Cs and retimers. You will collaborate with front‑end, analog/Ser Des, DFT, and packaging teams to drive tapeouts and ensure design convergence. The role requires solid experience with CTS, DRC/LVS, and access to Cadence Innovus or Synopsys ICC2, plus scripting in Python or Tcl to automate flows.
📌 Senior Asic Physical Design Lead For Soc Tapeouts (Toronto)
🏢 Qualcomm
📍 Toronto
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