16 Oct
|
Ciena
|
Boucherville
16 Oct
Ciena
Boucherville
Execute front end ASIC implementation, including synthesis and static timing analysis, for next-generation DSP programs. Develop timing constraints, perform equivalence verification, and collaborate with engineering teams.
📌 Senior Asic Synthesis And Sta Engineer - C$109,000 - C$174,000 A Year (Boucherville)
🏢 Ciena
📍 Boucherville