We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreHaving spent a decade or more working at the intersection of silicon, packaging, and board design, you know where good architectures succeed and where they fail. Evaluating package architectures, reviewing power delivery networks and bump maps, and turning SI/PI and EM analysis into sound engineering decisions are all part of your toolkit. When faced with ambiguity, you know how to focus on the issues that matter and keep complex programmes moving forward.At Synopsys, you'll lead package design for advanced IP test chips at the forefront of performance. Working with tools such as Ansys HFSS and collaborating across engineering teams, you'll help shape the technologies that enable the next generation of semiconductor products. Just as importantly, you'll bring the confidence to challenge assumptions, ask the right questions, and drive decisions that move the design forward.What You'll Be DoingLead four to six test-chip package designs per year from requirements definition through final delivery, coordinating across internal teams, customers, and external partnersDefine package requirements early in the design cycle, including bump maps, ball maps,



and layer stack-up decisions that optimize signal integrity and power integrity performancePerform hands‑on physical design and layout of advanced package substrates using industry-standard EDA toolsExtract electrical models from substrate designs using 3 D EM simulation tools like Ansys HFSS, and analyze them against SI and PI requirements to validate performanceGuide customers through package architecture evaluations and tradeoff analysis to identify implementation options that work for Synopsys IPResolve complex package design and integration issues by developing technically sound solutions that balance electrical performance, manufacturability, and costProvide regular project updates to management covering progress, technical risks, dependencies, mitigation plans, and decisions that need escalationThe Impact You Will HaveEnable successful tape‑outs of Synopsys IP test‑chips by ensuring package designs meet electrical and physical performance requirements from day oneReduce design iteration cycles and avoid costly respins by catching signal integrity and power integrity issues early through rigorous modeling and analysisExpand the range of package solutions available to Synopsys customers by evaluating new architectures and proving out their viability for high‑performance IPStrengthen customer relationships by providing expert guidance on package design decisions that directly affect their product successImprove design quality and efficiency across the team by establishing best practices for substrate layout, model extraction, and SI/PI validationAccelerate time‑to‑market for Synopsys IP by coordinating design phases, technical reviews,



and handoffs that keep projects moving without surprisesInfluence cross‑functional business‑unit projects by representing the package design perspective in technical decisions that affect multiple teamsWhat You'll Need10+ years of hands‑on experience in semiconductor package design, package substrate layout, electrical modeling, or closely related workAdvanced knowledge of circuit theory and transmission line behavior, with the ability to apply it to high‑speed package interconnect design and analysisDemonstrated experience building, validating, and interpreting 3 D electromagnetic models using Ansys HFSS or comparable simulation toolsStrong written and verbal communication skills in English, with the ability to explain complex technical tradeoffs to customers, partners, and cross‑functional teamsWorking knowledge of Windows and Linux environments used for engineering design and analysis workflowsBachelor's degree in electrical engineering, electronics engineering, or equivalent fieldExperience with advanced packaging technologies such as 2.5 D interposers, fan‑out wafer‑level packaging, or chiplet integration is a plusThe Team You'll Be Part OfYou will work with a highly skilled and supportive global team focused on ensuring Synopsys IP test‑chip packages meet electrical and physical performance requirements. Your recruiter will share more about the team structure and mission during the interview process.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial perks to cater to your needs. Our total rewards include both monetary and non‑monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.#J-18808-Ljbffr

📌 Sr Staff Package Design Engineer (Quebec City)
🏢 Synopsys
📍 Quebec City