Job Overview: Requirement/Must Have: 10 years of experience in RTL design using Verilog HDL.
Responsibilities:
Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for recent and modified functions. Responsible for linting and simulation of design.
Work with synthesis and backend teams for physical implementation. Qualification And Education: Bachelor's or Master's in Computer Engineering. Founded in 2010 and headquartered in the Washington, DC metro area, Cynet Systems Inc. is a leading staffing and recruiting powerhouse.
Proudly recognized as a nationally and locally certified diversity firm, Cynet delivers agile, scalable talent solutions across industries. With an active footprint in all 50 U.S. states and Canada, we support thousands of consultants through our expansive, high-performing recruitment engine operating across North America and Asia—ensuring speed, quality, and consistency in every hire.