Qualcomm seeks a skilled Memory Subsystem Design Verification Engineer in Vancouver or Markham to advance digital designs. In this pivotal role, drive verification efforts and collaborate on complex memory technologies. This position targets candidates with experience in digital design verification, particularly within memory subsystems.

You will develop comprehensive verification strategies, execute UVM-based testbenches, and analyze simulation failures. Strong skills in Verilog and SystemVerilog are essential, targeting those with a passion for memory architecture and protocols. Key Responsibilities:

- Develop verification strategies for complex RTL designs
- Create UVM-based testbenches and maintain reusable components




- Write and manage SystemVerilog Assertions for various validations
- Perform failure analysis using simulation tools
- Drive coverage closure through cooperative efforts Requirements:
- Bachelor’s or Master’s in Engineering or related field
- 3–10 years of experience in ASIC or SoC design verification
- Proficiency in Verilog, SystemVerilog, and UVM
- Strong debugging skills in reusable verification environments
- Solid understanding of digital design fundamentals Harness your verification expertise to help Qualcomm excel in memory technology.

📌 Memory Subsystem Verification Engineer at Qualcomm (Vancouver)
🏢 QUALCOMM
📍 Vancouver