Senior Design Verification Engineer (North York)

Senior Design Verification Engineer (North York)

15 Oct
|
SYMATICS TECHNOLOGY PTE.
|
North York

15 Oct

SYMATICS TECHNOLOGY PTE.

North York

About Symatics

Symatics is a Singapore-headquartered fabless semiconductor startup building the MPU, a deterministic AI inference accelerator for large language models. Instead of scheduling work at runtime, the MPU executes a compiler-generated static schedule across a large on-die compute array and a low-latency multi-chip fabric, on a 5nm-class node with commodity GDDR memory. The target is predictable, low-latency inference for MoE and agentic workloads at rack scale.

The founding team comes from ATI/AMD, Lightelligence, eTopus and the wider GPU, SerDes and AI-silicon community. Toronto is our MPU design centre; Hsinchu is the centre for the fabric switch.

What you will do

Build the verification environment and sign-off methodology for a deterministic inference ASIC, where cycle-exact behaviour against a golden model is the pass criterion.

- Architect UVM 1.2 testbenches at block, subsystem and full-chip level
- Own test plans, functional/code coverage closure and regression infrastructure




- Integrate the C/Python golden model as a cycle- and bit-accurate reference (DPI-C); build scoreboards and checkers
- Verify high-speed interfaces with commercial VIP (PCIe Gen5/6, GDDR)
- Drive formal (connectivity, CDC, property checking), gate-level sim and emulation/FPGA acceleration of regressions
- Define acceptance criteria for RTL deliverables from external design partners

What we are looking for

- BS/MS EE/CE; 7+ years DV with full-chip sign-off on at least two tapeouts
- Expert SystemVerilog/UVM; strong Python/scripting for regression and triage automation
- Hands-on with coverage-driven verification and at least one formal tool
- Track record of building an environment from scratch, not just inheriting one

Nice to have

- Emulation (Palladium / Zebu / Veloce)
- Verification of compute arrays, GPUs or network switches
- Use of AI-assisted coding tools in a DV flow

Pay: $160,000.00-$200,000.00 per year

Advantages:

- Flexible schedule

Work Location: In person

📌 Senior Design Verification Engineer (North York)
🏢 SYMATICS TECHNOLOGY PTE.
📍 North York

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