A leading semiconductor company is seeking an RTL/FPGA Design Engineer with over 15 years of experience. The ideal candidate should have a bachelor's degree in engineering or computer science and possess excellent skills in RTL design using Verilog and System Verilog.
Key responsibilities include working with EDA tools and knowledge of networking standards. This contract position offers a pay range of CA$110.00/hr to CA$135.00/hr.
📌 Senior Rtl/fpga Design Eng Verilog, Vivado, Cdc Contract Montreal
🏢 LanceSoft
📍 Montreal
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