Senior Asic Verification Engineer Systemverilog & Uvm Quebec City (Canada)

Senior Asic Verification Engineer Systemverilog & Uvm Quebec City (Canada)

13 Oct
|
TSMC - Taiwan Semiconductor Manufacturing
|
Canada

13 Oct

TSMC - Taiwan Semiconductor Manufacturing

Canada

TSMC Design Technology Canada Inc. (TDTC) in Ottawa is seeking a Digital Verification Engineer to validate digital circuits, develop test benches and perform functional verification for manufacturing/tester patterns.
The candidate will contribute to verification methodology customization and help improve the group’s EDA capabilities, working with Synopsys VCS or Cadence Incisive in a Unix/Linux setting.
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📌 Senior Asic Verification Engineer Systemverilog & Uvm Quebec City (Canada)
🏢 TSMC - Taiwan Semiconductor Manufacturing
📍 Canada

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