Elevate your career as a Design Verification Engineer with Qualcomm in Canada. Focus on comprehensive pre-silicon test planning and automation to ensure effective digital power IP verification. This role involves participation in the complete verification lifecycle, utilizing advanced verification methodologies like SystemVerilog-UVM.

You will engage in coverage development, assertion model creation, and formal verification processes. Ideal for candidates with a solid foundation in ASIC design and verification techniques, this position also promotes improved verification efficiency. Key Responsibilities:

- Develop comprehensive pre-silicon test plans for digital power IPs
- Utilize SystemVerilog-UVM for testbench development
- Implement coverage and assertion models for verification




- Automate processes to enhance verification workflow
- Engage in post-silicon support for design validation Requirements:
- Bachelor's degree and 2+ years in ASIC design/verification
- Proficiency in RTL languages such as SystemVerilog, Verilog, or VHDL
- Familiarity with UVM or similar verification methodologies
- Knowledge of scripting languages like Perl or Python
- Experience in developing block-level testbench environments Bring your expertise in ASIC design and verification techniques to Qualcomm as a Design Verification Engineer.

📌 Design Verification Engineer at Qualcomm (Vancouver)
🏢 QUALCOMM
📍 Vancouver