Ciena Corporation in Ottawa is seeking a senior ASIC backend designer to drive physical design, floorplanning, and timing closure for high-performance networks. You will work with RTL teams to integrate analog blocks and optimize PPA while leveraging advanced EDA flows. The role emphasizes scripting, formal verification, and STA analysis to ensure signoff-quality results on tight submicron nodes. A robust collaboration with tool vendors and cross-functional teams is essential.