Ciena Corporation is seeking an experienced FPGA/ASIC verification engineer to lead chip-level verification efforts for complex FPGA designs. You will establish verification methodologies, develop testbenches, and drive regression triage and bug resolution while mentoring junior engineers in best practices. The role requires 8+ years of verification experience, SystemVerilog/UVM proficiency, and a strong background with PCIe, I2C, and SPI interfaces in a Linux/Unix workplace.
📌 Senior FPGA Verification Architect & Mentor (Ottawa)
🏢 Ciena
📍 Ottawa