Must work in office in Vancouver or Toronto.

Key Responsibilities
Execute RTL synthesis for complex ASIC and SoC designs using Cadence Genus.
Optimize designs for power, performance, and area (PPA) throughout the synthesis and physical design flow.
Develop and improve floorplans using Cadence Innovus, ensuring effective utilization and routing.
Collaborate with RTL, architecture, and design teams to provide feedback on timing, constraints, and implementation strategies.
Partner with physical implementation and place-and-route teams to achieve timing closure and design quality goals.
Analyze timing challenges, identify critical paths, and recommend design improvements to improve convergence.
Support physical implementation activities from synthesis through implementation while maintaining design quality and schedule objectives.

Required Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related discipline.
5+ years of experience in ASIC or SoC Physical Design.




Hands-on expertise with Cadence Genus for synthesis and Cadence Innovus for floorplanning and implementation.
Experience working on large, high-performance semiconductor designs with demanding timing requirements.
Solid knowledge of synthesis, timing analysis, physical implementation, and PPA optimization.
Experience with advanced semiconductor process technologies such as 5nm, 3nm, or newer.
Excellent communication skills and the ability to work effectively with RTL, architecture, physical design, and implementation teams.
Preferred Qualifications
Experience supporting complex SoC, AI, HPC, or accelerator designs.
Strong understanding of timing closure methodologies and synthesis-to-implementation correlation.
Familiarity with advanced implementation flows, design constraints, and physical optimization techniques.
Proven ability to collaborate with globally distributed engineering teams to deliver successful silicon implementations.

📌 Physical Design Engineer Toronto
🏢 Terranova Talent Solutions
📍 Toronto