Elevate your career as a Design Verification Engineer at Actalent, specializing in Ethernet and networking IP for advanced technology applications. This role is fully onsite in Ottawa, focusing on cutting-edge SoC solutions.

Join an experienced R&D; team at Actalent, where you'll architect, design, implement, and verify networking IP in a collaborative environment. You will work on cutting-edge projects for automotive, industrial, and edge computing markets. Your proficiency in System Verilog and UVM verification will be key to ensuring the successful delivery of high-quality IP.

Key Responsibilities:
• Architect and implement Ethernet/networking IP for SoCs
• Develop UVM-based verification environments and tests




• Analyze performance and trade-offs in design methodologies
• Collaborate with architecture and design teams for project outcomes
• Produce documentation and review coverage metrics

Requirements:
• 5-15 years in IP & SoC development
• Proficiency in System Verilog and UVM
• Familiarity with EDA tools and scripting languages
• Experience with design verification infrastructure
• Bachelor’s degree in relevant technical field

Make a significant impact in the evolving fields of networking and SoC technology.
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📌 Design Verification Engineer in Ottawa (Quebec City)
🏢 Actalent
📍 Quebec City