Synopsys, Inc. seeks a visionary technical leader to guide SERDES PHY IP development from concept to customer-ready products. You will oversee a diverse engineering team, collaborating across architecture, verification, physical implementation, and firmware to meet aggressive timing, power, and performance targets. We value deep expertise in Verilog/SystemVerilog, frontend design flows, and a proven record of mentoring top talent.
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📌 Senior ASIC Digital Design Lead — SERDES PHY IP (Winnipeg)
🏢 Synopsys
📍 Winnipeg
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