Qualcomm seeks a Design Verification Engineer to enhance digital power IP verification. Engage in pre-silicon planning and automation in a dynamic environment.

As part of the Engineering Group at Qualcomm Canada, you'll cover the complete verification lifecycle from concept to silicon. Key responsibilities include developing testbenches using SystemVerilog-UVM, coverage development, and formal verification. This role champions innovative verification methodologies while improving overall efficiency.

Key Responsibilities:
• Develop pre-silicon test plans for digital power IP
• Create advanced testbenches using SystemVerilog-UVM
• Engage in coverage and assertion model development
• Implement a power-aware UPF verification flow




• Automate processes to enhance verification efficiency

Requirements:
• Bachelor's degree in Engineering or Science with 2+ years in ASIC verification
• Master’s degree preferred with 1+ year of relevant experience
• Proficient in SystemVerilog, digital design, and RTL languages
• Experience with UVM or OVM verification methodologies
• Scripting skills in Perl or Python are a plus

Drive cutting-edge verification technologies as a vital part of Qualcomm’s creative team.
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📌 Design Verification Engineer at Qualcomm (Ontario)
🏢 QUALCOMM
📍 Ontario