Compiler Engineer — Mapping & Scheduling (North York)

Compiler Engineer — Mapping & Scheduling (North York)

07 Oct
|
SYMATICS TECHNOLOGY PTE.
|
North York

07 Oct

SYMATICS TECHNOLOGY PTE.

North York

About Symatics

Symatics is a Singapore-headquartered fabless semiconductor startup building the MPU, a deterministic AI inference accelerator for large language models. Instead of scheduling work at runtime, the MPU executes a compiler-generated static schedule across a large on-die compute array and a low-latency multi-chip fabric, on a 5nm-class node with commodity GDDR memory. The target is predictable, low-latency inference for MoE and agentic workloads at rack scale.

The founding team comes from ATI/AMD, Lightelligence, eTopus and the wider GPU, SerDes and AI-silicon community. Toronto is our MPU design centre; Hsinchu is the centre for the fabric switch.

What you will do

- Design and implement graph partitioning, placement and static scheduling of LLM workloads onto a large spatial compute array across many chips
- Lower from PyTorch / ONNX / MLIR-level IR to our instruction set and configuration images
- Model and optimise memory placement, weight layout and inter-chip communication schedules with cycle-level determinism




- Implement quantisation-aware lowering (FP8 / INT8 / INT4) with the numerics team
- Validate compiler output against the golden model and FPGA prototype; build the regression suite
- Work directly with hardware architects on ISA and schedule-format co-design

What we are looking for

- MS/PhD CS/CE or equivalent; 5+ years building production compilers for accelerators, GPUs, FPGAs or DSPs
- Solid C++ and Python; hands-on with MLIR, LLVM, TVM, XLA, IREE or Triton
- Solid algorithms background: graph partitioning, scheduling, ILP/constraint solving, polyhedral or similar
- Understanding of transformer / MoE model structure and inference dataflow

Nice to have

- Statically scheduled or dataflow targets (Groq, Cerebras, Tenstorrent, SambaNova, CGRA / HLS tools)
- Place-and-route or EDA algorithm background
- University of Toronto / Waterloo compiler or FPGA CAD research lineage

Pay: $180,000.00-$230,000.00 per year

Work Location: In person

📌 Compiler Engineer — Mapping & Scheduling (North York)
🏢 SYMATICS TECHNOLOGY PTE.
📍 North York

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