Hardware / Performance Architect (North York)

Hardware / Performance Architect (North York)

07 Oct
|
SYMATICS TECHNOLOGY PTE.
|
North York

07 Oct

SYMATICS TECHNOLOGY PTE.

North York

About Symatics

Symatics is a Singapore-headquartered fabless semiconductor startup building the MPU, a deterministic AI inference accelerator for large language models. Instead of scheduling work at runtime, the MPU executes a compiler-generated static schedule across a large on-die compute array and a low-latency multi-chip fabric, on a 5nm-class node with commodity GDDR memory. The target is predictable, low-latency inference for MoE and agentic workloads at rack scale.

The founding team comes from ATI/AMD, Lightelligence, eTopus and the wider GPU, SerDes and AI-silicon community. Toronto is our MPU design centre; Hsinchu is the centre for the fabric switch.

What you will do

Own micro-architecture and performance modelling for a large, regular compute-array inference ASIC. You turn system-level intent into block specs the RTL and compiler teams can build against.

- Define micro-architecture for compute array, memory subsystem and chip-to-chip interconnect; write block-level specs
- Build and maintain the performance model (Python/C++)



and the bit-accurate C/golden model; correlate against RTL and FPGA
- Run PPA trade-offs (area, power, bandwidth, latency) on a 5nm-class node with GDDR-class memory and PCIe Gen6-class SerDes
- Co-design with the compiler team: instruction set, static schedule format, memory map
- Technical lead on architecture reviews with our design-service partners

What we are looking for

- MS/PhD EE/CE; 10+ years in GPU, AI accelerator, network or CPU architecture
- Shipped silicon where you owned a major block or subsystem spec
- Strong in performance modelling, memory hierarchy and interconnect bandwidth/latency analysis
- Working knowledge of transformer / MoE inference dataflow

Nice to have

- Dataflow, spatial or statically scheduled architectures (Groq, Cerebras, Tenstorrent, SambaNova-style)
- Chiplet / UCIe, multi-die system partitioning

Pay: $200,000.00-$250,000.00 per year

Benefits:

- Adaptable schedule

Work Location: In person

📌 Hardware / Performance Architect (North York)
🏢 SYMATICS TECHNOLOGY PTE.
📍 North York

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