About Symatics

Symatics is a Singapore-headquartered fabless semiconductor startup building the MPU, a deterministic AI inference accelerator for large language models. Instead of scheduling work at runtime, the MPU executes a compiler-generated static schedule across a large on-die compute array and a low-latency multi-chip fabric, on a 5nm-class node with commodity GDDR memory. The target is predictable, low-latency inference for MoE and agentic workloads at rack scale.

The founding team comes from ATI/AMD, Lightelligence, eTopus and the wider GPU, SerDes and AI-silicon community. Toronto is our MPU design centre; Hsinchu is the centre for the fabric switch.

What you will do

Design and deliver production RTL for the MPU compute die, working from architecture specs through to handoff for physical design.

- Micro-architect and code SystemVerilog RTL for compute-unit array, control/sequencing, memory controllers and high-speed interface wrappers
- Integrate third-party IP: PCIe Gen5/6 controller + PHY, GDDR PHY, PLLs,



management CPU subsystem
- Own lint, CDC/RDC, synthesis constraints and timing closure feedback with the physical design team
- Design for a highly replicated, tiled array: hierarchy, clock/reset distribution, DFT hooks, power intent (UPF)
- Support FPGA prototyping and bring-up of your blocks

What we are looking for

- BS/MS EE/CE; 7+ years RTL design with at least two tapeouts on 16nm or below
- Expert SystemVerilog; solid on synthesis, STA concepts, CDC, low-power design
- Experience integrating high-speed SerDes-based interfaces or memory interfaces
- Comfortable working with remote design-service partners across time zones

Nice to have

- GPU / AI accelerator / switch ASIC datapath design
- Large-die (400 mm2+) experience; tiled or array-based floorplans

Pay: $160,000.00-$200,000.00 per year

Work Location: In person

📌 Senior RTL Design Engineer (North York)
🏢 SYMATICS TECHNOLOGY PTE.
📍 North York