Senior Technical Staff Engineer – Analog Design

Microchip’s Timing and Communication Group (TCG) is seeking a Senior Technical Staff Engineer – Analog Design to provide technical leadership and architectural direction across the development of advanced analog and mixed‑signal IP for next‑generation timing solutions.

Responsibilities

• Define architecture, specifications, and design methodologies for high‑performance analog IP, including PLLs, DLLs, ADCs, DACs, filters, high‑speed I/O interfaces, and related circuits used in TCG products.
• Drive top‑level mixed‑signal system architecture to ensure robust integration of analog IP within complex SoC environments.
• Influence long‑term analog IP direction and contribute to product roadmap discussions.
• Provide senior‑level technical guidance to analog design teams through design reviews, modeling strategy, simulation methodology, and silicon bring‑up.
• Serve as a technical resource and mentor for junior and mid‑level designers, supporting sound design decisions and skill development.
• Influence design trade‑offs, verification approaches, and modeling strategies across multiple projects.
• Lead transistor‑level design and advanced simulations across process corners and operating conditions.
• Develop and review behavioral and Verilog‑A models to support efficient mixed‑signal SoC simulation.
• Guide silicon validation, characterization, test planning, and system‑level laboratory evaluation.
• Partner closely with architects,
  
  
  
  digital and mixed‑signal designers, layout teams, product engineers, and multi‑site engineering groups.
• Support first‑pass silicon success through disciplined design execution and cross‑team coordination.

Requirements / Qualifications

• Master’s degree or Doctorate in Electrical Engineering or a closely related field.
• 10+ years of industry experience in analog and mixed‑signal IC design.
• Proven experience designing high‑speed and analog circuits such as PLLs/DLLs, ADCs/DACs, filters, and high‑speed I/O.
• Robust fundamentals in device physics, circuit theory, and layout‑aware design.
• Extensive experience with Cadence IC design tools and flows.
• Hands‑on experience with scripting and automation (e.g., Skill, Python, Perl, Tcl).
• Strong communication skills and experience working effectively in multi‑site engineering teams.

Additional Experience That Adds Value

• Advanced academic study or research in analog or mixed‑signal design that strengthens system‑level insight or modeling approaches.
• Experience applying research concepts to practical, production‑ready silicon.
• Expertise in mixed‑signal system‑level design and architecture.
• Strong proficiency in Verilog‑A for analog behavioral modeling.
• Experience with silicon bring‑up, debug, and characterization in lab environments.
• Exposure to MEMS analog interface circuits.

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