Nuvacore is building ground-up CPU silicon for next-generation compute workloads. Our software organization works at the intersection of CPU architecture, silicon design, firmware, operating systems, toolchains, and platform software — developing the compiler toolchains, OS enablement, firmware, and validation infrastructure that ensure new processor capabilities are fully realized in software. We're hiring a Compiler & Toolchain Engineer to accelerate and harden the toolchains and libraries that help unlock the performance of Nuvacore's processors.

The Role

As a Compiler & Toolchain Engineer, you'll be a core member of the team building and maintaining Nuvacore's compiler and toolchain stack across GCC and LLVM along with core libraries and runtime environments. You'll work close to the metal — implementing machine models for our microarchitecture, chasing down codegen correctness and performance issues, and partnering directly with CPU architects to extract every bit of performance possible. You will work closely with our performance engineers to develop an understanding of key performance issues in real-world applications and strategies for optimizing software, libraries and the microarchitecture.

What You'll Own

Design, implement, and maintain compiler backend support (instruction selection, scheduling, register allocation, code generation) for Nuvacore's ISA across GCC and/or LLVM

Diagnose and resolve codegen correctness bugs and performance regressions across the toolchain, from source down to generated machine code

Track and integrate upstream LLVM/GCC changes, and contribute upstream where it benefits the broader ecosystem

Drive toolchain architecture decisions that span the software/hardware boundary and set technical direction for the compiler team





Performance optimization of system libraries and dynamic language environments

Requirements — Must Have

15+ years of professional experience working on compiler internals — frontend, middle-end, or backend — in LLVM and/or GCC

Strong understanding of compiler backend construction: instruction selection, register allocation, instruction scheduling, and code generation

Low-level programming experience targeting x86, ARM, or RISC-V architectures

Proven experience debugging functional and performance issues in large, complex software systems

Experience working within contemporary, automated software development methodologies (CI/CD, automated testing, code review tooling)

Strong written and verbal communication skills

Demonstrated ability to collaborate across functional teams and work flexibly across domains (compiler, architecture, firmware)

Experience with performance analysis of large scale system-level applications including JIT environments and multiple languages

Requirements — Nice to Have

Upstream contributions to LLVM, GCC, or binutils

Compiler-level performance optimization tuned to a specific microarchitecture

Experience with simulators or instruction set simulators (QEMU, ISS) for toolchain bring-up and validation

Experience bringing up a toolchain for new silicon, from pre-tapeout simulation through post-silicon validation

Prior experience at a CPU or silicon design company

What Success Looks Like

Development of machine models for the Nuvacore microarchitecture

Meaningful performance analysis and optimization of key workloads

Toolchain regressions are caught by automated test infrastructure before they reach downstream firmware or OS teams

Architecture and firmware teams treat you as a trusted technical partner on compiler-related design tradeoffs

📌 ToolChain Engineer Software United States / India / Canada · Hybrid (Toronto)
🏢 NUVACORE
📍 Toronto