We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being—on and off the job. Join a team focused on the design and integration of custom mixed-signal macros within an ASIC flow for next-generation high-baud-rate optical modems.

Work involves advanced nanoscale CMOS technologies that enable high-performance optical and electrical interfaces. The role provides opportunities to contribute to mixed-signal circuit design and IP integration activities in a collaborative engineering environment. Utilize knowledge of electronics, mathematics, VLSI design, and computer-aided design tools to solve engineering design challenges.

Generate representations of mixed-signal blocks for the digital design team, including Verilog, Library Exchange Format, Liberty timing files, documentation, preliminary and final layout files, and SPICE netlists for chip-level LVS as part of IP integration activities. Develop understanding of the design and place-and-route of macro-level standard cell interfaces to facilitate analog-digital timing handoff and static timing analysis. Contribute to digital integrated circuit design using standard cell libraries and develop design-for-test solutions and models aligned with ASIC test methodologies.





Completed a bachelor’s or master’s degree in electrical or computing engineering.

Experience: Previous internship, co-op, or applied project experience relevant to the role. A solid understanding of digital design, including Verilog/RTL, place-and-route, and static timing analysis. Scripting in Python and Cadence Skill language Confident working in both Windows and Linux environments Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission.

In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence. At Ciena, we are committed to building and fostering an workplace in which our employees feel respected, valued, and heard.

Ciena values the diversity of its workforce and respects its employees as individuals. Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

📌 Mixed Signal IP Integration Engineer - New Grad (Ottawa)
🏢 Ciena
📍 Ottawa