Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D; capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You have spent years building verification environments for complex digital designs where mistakes show up as silicon respins or customer escalations. The difference between a PHY that passes regression and one that works in production is something you understand deeply, and it shapes how you write testplans, model coverage, and design infrastructure. You have inherited enough unmaintainable code to know what matters when a project needs to scale across multiple product generations.

Technical reviews matter to you because that is where you can catch verification risks before they become schedule problems. Develop comprehensive testplans and functional coverage models for training firmware running on RTL models of memory PHYs Create test cases that cover success paths, corner cases, and negative scenarios based on standard specifications and feature enhancements Debug complex issues across firmware, RTL, and testbench layers using simulation and waveform analysis tools Participate in technical reviews with architecture and implementation teams to influence design decisions from a verification perspective Research and evaluate emerging technologies in virtual prototyping and emulation to improve team efficiency, throughput, and quality Mentor junior engineers on testbench design, debugging techniques,



and verification methodology while collaborating with other principal-level engineers on verification strategy Your testplans and coverage models will define the quality bar for memory interface IP that powers next-generation products across the industry The testbench infrastructure you build will accelerate verification cycles and enable the team to scale as recent product lines come online Your debugging expertise will catch critical issues before they reach customers, protecting both product schedules and Synopsys reputation Technical reviews you contribute to will shape architecture decisions early, preventing costly verification bottlenecks downstream Your work with customers (on simulation debug or post-silicon bring-up debug) will strengthen their confidence in our IP and inform future product roadmaps BSc in Electrical Engineering, Computer Engineering, or related field with 12+ years of verification experience, MSc with 10+ years, or PhD with 8+ years Deep proficiency in SystemVerilog and UVM, with a track record of building reusable testbench components and verification environments Solid understanding of C and experience with software/hardware co-simulation Experience with assertion-based verification, coverage analysis, and protocol-oriented performance debug Comfort working in Linux environments with scripting for regression systems, build automation, and source control workflows Experience with virtual prototyping or emulation platforms is a strong plus, as is knowledge of LPDDR5/5X and LPDDR6 or other memory interface standards You can read a functional spec and immediately start sketching out the test scenarios that will stress the design in ways the architects did not anticipate You bring a point of view to design reviews and you are not afraid to flag a verification risk even if it means pushing back on a schedule You explain complex verification trade-offs clearly enough that an architect or project manager understands the risk without needing a deep dive into UVM internals The team is international, with members collaborating across multiple time zones to deliver IP that ships into high-volume products. You will work alongside other principal-level verification engineers, contributing to verification strategy while also building and executing on testplans.

The group values technical depth, rigorous methodology, and the kind of verification work that actually prevents customer issues rather than just checking compliance boxes.

📌 Principal FPGA Verification Engineer (Quebec)
🏢 Synopsys
📍 Quebec